Various methods and systems are known in the art for accessing and processing data that are stored in memory. Some known methods and systems use content-addressable techniques, in which stored data are addressed by their content, rather than by storage address, Content-addressable techniques are also sometimes referred to as associative processing techniques.
A parallel architecture for machine vision based on an associative processing approach is described, for example, in a Ph.D. thesis by Akerib, entitled “Associative Real-Time Vision Machine” (Department of Applied Mathematics and Computer Science, Weizmann Institute of Science, Rehovot, Israel, March, 1992), which is incorporated herein by reference.
The most common types of memory devices currently in use are random access memory (RAM) devices, such as dynamic random access memory (DRAM) and static random access memory (SRAM). A RAM device allows a memory circuit to read and write data by specifying the addresses of the data in the memory.
Content addressable memory (CAM) is a special type of memory device, which is typically used to accelerate applications requiring fast content searching. Searches in CAM devices are performed by simultaneously comparing an input data value (in the form of a string of bits in a comparand register) against the pre-stored entries in the memory. When the entry stored in a CAM memory location matches the data in the comparand register, a local match detection circuit returns a match indication. In addition, the CAM may return an address or addresses associated with the matched data. Binary CAM uses data search words composed entirely of ones and zeroes. Ternary CAM allows a third matching state of “X” or “Don't Care,” typically by adding a mask bit to every memory cell.
Some devices may include both RAM and CAM segments. For example, U.S. Pat. No. 3,685,020, whose disclosure is incorporated herein by reference, describes a compound memory that includes a random access array with an associative array as part of its accessing means. A match in the associative array between an effective address, identifying an addressed information block, and an associative array word directly energizes corresponding random access array locations that contain the addressed information block.
As another example, U.S. Pat. No. 5,706,224, whose disclosure is incorporated herein by reference, describes a semiconductor memory device that is partitionable into RAM and CAM subfields. Each of the CAM cells comprises a RAM cell attached to a comparator. The user may partition the memory array into a number of segments, some or all of which may be configured to function as simple RAM, rather than as CAM.
U.S. Pat. No. 6,195,738, whose disclosure is incorporated herein by reference, describes an architecture combining an associative processor memory array and a random access memory, which is used to store temporary results and parameters. Parallel communication between thousands of memory words in the associative memory array and the random access memory is provided via logic hardware.